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Graphics FE Implementation Engineer
Austin, TX
Job Description
Summary
Posted: Dec 19, 2023
Role Number:200530192
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Engineering group, you'll help design and manufacture our next-generation, high-performance, power-efficient processors! You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. As part of the GPU FE Implementation team, you'll be responsible for crafting and building a GPU that enriches the lives of millions of people every day!
Key Qualifications
Description
You will be responsible for RTL to netlist generation working closely with the RTL and Physical design teams. You will also deliver key netlist quality achievements for your partition, engage in Lint, CDC, Logic equivalence checks and support ECO generation activities. Through this collaboration, you will deliver the best-in-class GPU's for the best consumer products. If you're ready to help chart the future of Apple Silicon, we'd love to talk to you.
Education & Experience
We are looking for candidates with BS + 0 years of relevant experience.
Additional Requirements
Additional Requirements
Posted: Dec 19, 2023
Role Number:200530192
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Engineering group, you'll help design and manufacture our next-generation, high-performance, power-efficient processors! You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. As part of the GPU FE Implementation team, you'll be responsible for crafting and building a GPU that enriches the lives of millions of people every day!
Key Qualifications
- We are looking for candidates with relevant coursework in Computer Architecture, Digital Logic Design and CMOS VLSI design.
- Understanding of CMOS device characteristics for area/timing/power tradeoffs.
- Ability to read and understand Verilog and System Verilog.
- Knowledge of static timing analysis concepts (setup and hold timing) and metastability concerns.
- Proficient in at least one scripting language.
- Ability to work with multiple teams across different sites.
- Preferred, but not required:
- Exposure to industry standard rtl2gds tools for synthesis, place and route, static timing analysis.
- Exposure to Clock/Reset domain crossing principles.
- Familiarity with DFT methodologies.
Description
You will be responsible for RTL to netlist generation working closely with the RTL and Physical design teams. You will also deliver key netlist quality achievements for your partition, engage in Lint, CDC, Logic equivalence checks and support ECO generation activities. Through this collaboration, you will deliver the best-in-class GPU's for the best consumer products. If you're ready to help chart the future of Apple Silicon, we'd love to talk to you.
Education & Experience
We are looking for candidates with BS + 0 years of relevant experience.
Additional Requirements
Additional Requirements
Job Summary
Company
Start Date
As soon as possible
Employment Term and Type
Regular, Full Time
Required Education
Bachelor's Degree
Required Experience
20+ years
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